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Memory architecture
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#	Item
681	Smart Thread Scheduling is the Key for OLTP Pınar Tözün Ippokratis Pandis EPFL Add to Reading List Source URL: tinytocs.org Language: English - Date: 2013-04-02 18:41:25 Microprocessors Computer architecture Parallel computing CPU cache Computer memory Online transaction processing Multi-core processor Cache Computer hardware Computing Central processing unit
682	Inside L4/MIPS Anatomy of a High-Performance Microkernel Gernot Heiser Version[removed]syscalls+scheduling) of January 30, [removed]removed] Add to Reading List Source URL: www.cse.unsw.edu.au Language: English - Date: 2001-03-05 23:47:41 Virtual memory L4 microkernel family Memory management unit Control flow Microkernel Thread Kernel Page Gernot Heiser Computer architecture Computing Central processing unit
683	Location-Based Memory Fences Edya Ladan-Mozes I-Ting Angelina Lee Dmitry Vyukov∗ Add to Reading List Source URL: www.cse.wustl.edu Language: English - Date: 2014-08-27 02:16:24 Central processing unit Computer memory Concurrency control Microprocessors Memory barrier CPU cache Parallel computing Linearizability Microarchitecture Computer architecture Computing Computer hardware
684	AMULET3i An Asynchronous System-on-Chip Jim Garside HotChips 12 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:37:57 Computer architecture Computing Dynamic random-access memory AMULET microprocessor Integrated circuits Atmel AVR Intel Computer hardware Computer memory Microcontrollers
685	PA-RISC 1.1 I/O Firmware Architecture Reference Specification Version[removed]Printed in U.S.A. March 7, 1999 Add to Reading List Source URL: ftp.parisc-linux.org Language: English - Date: 2001-11-21 18:15:38 Module Computer memory Microcontrollers
686	SYSTEM V APPLICATION BINARY INTERFACE PowerPC Processor Supplement by Steve Zucker, SunSoft Add to Reading List Source URL: uclibc.org Language: English - Date: 2012-05-05 03:48:31 Instruction set architectures Computer memory Data transmission Endianness Metaphors PowerPC Bit numbering Application binary interface Debian Computer architecture Software Computing
687	HC17.S8T4.Xbox 360 System Architecture.ppt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:48:15 Central processing unit Computer memory Computing Computer hardware CPU cache Cache
688	Associative Memory Networks for Beyond Boolean Computing Danny Voils Portland State University January 27, 2014 Add to Reading List Source URL: web.cecs.pdx.edu Language: English - Date: 2014-01-28 14:57:16 Computer memory Computer networking Content-addressable memory Computer Heterogeneous computing Scalability Multi-core processor ACT-R Computing Computer architecture Electronics
689	Ò FOURTH GENERATION 64-BIT RISC MICROPROCESSOR Add to Reading List Source URL: www.sgistuff.net Language: English - Date: 2011-07-08 05:35:18 Central processing unit R4600 Computer memory R4000 Virtual memory MIPS architecture CPU cache Memory management unit 64-bit Computer hardware Computer architecture Computing
690	A RISC Processor for SR8000: Accelerating Large Scale Scientific Computing with SMP Toshihiko Kurihara, Eiki Kamada, Kentaro Shimada, Teruhisa Shimizu Hitachi, Ltd. Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:49:03 Central processing unit CPU cache Cache Computer memory Superscalar R8000 Instruction set RHPPC RISC Single Chip Computer architecture Computer hardware Computing

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